Robert D. Clark and his coauthors worked in an deep study which is an invited perspective on the new process technologies that will need to be developed in order to enable future semiconductor device scaling. It’s in the most recent issue of APL Materials.
This paper presents an overview and perspective on processing technologies required for continued scaling of leading edge and emerging semiconductor devices. They introduce the main drivers and trends affecting future semiconductor device scaling and provide examples of emerging devices and architectures that may be implemented within the next 10-20 yr. They summarize multiple active areas of research to explain how future thin film deposition, etch, and patterning technologies can enable 3D (vertical) power, performance, area, and cost scaling. Emerging and new process technologies will be required to enable improved contacts, scaled and future devices and interconnects, monolithic 3D integration, and new computing architectures. These process technologies are explained and discussed with a focus on opportunities for continued improvement and innovation.
FIG. 1.Illustration of the migration to 3D devices and 3D architectures taking place in the semiconductor industry. (note: IDM is an integrated device maker).
FIG. 2.Illustration of a self-aligned quadruple patterning (SAQP) flow with unidirectional lines and multiple cut masks. Dense lines and space patterns are initially formed by SAQP, and then multiple cuts or trim masks with very fine isolated features are used to cut the lines into useful device features or wiring. The EPE is a function of the critical dimension (CD) variation as well as the pattern overlay (OL) error for each mask.
FIG. 3.Cross-sectional schematic illustrating the multi-color approach to SAGC integration. GC and SD arrows indicate relative EPE tolerances for gate contact (GC) and source/drain (SD) contact placement, respectively. The gate cap and SD cap are dielectric capping layers that can be etched away selectively,7 so if an SD contact lands partially on a gate cap, the gate cap will prevent a short. See also Fig. 4.
Source: https://aip.scitation.org
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