{"id":2403,"date":"2018-06-13T13:33:26","date_gmt":"2018-06-13T13:33:26","guid":{"rendered":"https:\/\/athis-consulting.com\/news\/?p=2403"},"modified":"2018-09-14T19:49:36","modified_gmt":"2018-09-14T19:49:36","slug":"advanced-packaging-confusion","status":"publish","type":"post","link":"https:\/\/athis-technologies.com\/news\/innovation\/manufacturing\/2018\/advanced-packaging-confusion\/","title":{"rendered":"Advanced Packaging Confusion"},"content":{"rendered":"
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An interesting article from\u00a0 Ed Sterling at\u00a0semiengineering.com.<\/p>\n

Advanced packaging is exploding in all directions. There are more chipmakers utilizing different packaging options, more options for the packages themselves, and a confusing array of descriptions and names being used for all of these.<\/p>\n

Several years ago, there were basically two options on the table, 3D-ICs<\/a> and 2.5D<\/a>. But as chipmakers began understanding the difficulty, cost and reduced benefits of device scaling, advanced packaging really began taking off. The growing success of this approach has created its own set of problems, though. There now are multiple flavors of 2.5D, as well as multiple types of fan-outs<\/a>, fan-ins, system-in-package, package-on-package, flip chips, and various different bridge technologies. Add to that list package-less approaches, wafer-level packaging, and die-on-die-on-wafer. There is even talk of panel-level packaging.<\/p>\n

\u201cThe problem is that there are so many permutations with advanced packaging that it\u2019s basically endless,\u201d said Jan Vardaman, president of TechSearch International. \u201cIt used to be wirebonds and leadframes. Now we have area arrays and chip scale. The package can be leaded, or the peripheral can be leaded. And with arrays you have BG (ball grid), CSP (chip-scale package), wafer-level and a ton of fan-outs. That\u2019s one of the big problems. There are too many choices.\u201d<\/p>\n

Vardaman has a growing amount of support on that point.<\/p>\n

\u201cMany companies want to put a specific name or brand name to this technology,\u201d said William Chen, ASE<\/a> fellow and senior technical advisor. \u201cThat\u2019s very confusing. We have many different technologies with fine-tuned differences. But we don\u2019t need this kind of confusion bred into a system, and as we go forward we my need to put this into a framework and eventually go to a standard approach. This is why ASE has tried to do as much as possible not to invent names and terms.\u201d<\/p>\n

The road to better definitions<\/strong>
\nHaving a long list of packaging options isn\u2019t necessarily bad, because it allows chipmakers and OEMs to develop more customized multi-chip solutions. But having too many naming conventions is another matter, entirely. In fact, IEEE has begun making overtures to tighten up the nomenclature around 2.5D, where there are options for 2.1D using organic interposers and 2.7\/2.75D using bridges. There also are side-by-side and vertical implementations of 2.5D, as well as pillars on interposers.<\/p>\n

Raja Swaminathan, IEEE\u2019s roadmap author and an industry expert on packaging, said there is an effort to roll up all of the 2.x nomenclature under 2DO, for both chip-first and chip-last organic-based connectors, and 2DS, for passive silicon-based packages, with or without TSVs.<\/p>\n

\u201cOn package is higher-density compared to side-by-side,\u201d Swaminathan said. \u201cBut the goal is to get these architectures under a single umbrella so that you can define what these architectures mean and then compare different metrics.\u201d<\/p>\n

\"\"<\/a>
\nFig. 1: 2DO vs. 2DS. Source: IEEE\/Swaminathan<\/strong><\/p>\n

IEEE introduced that concept at IEEE\u2019s Electronic Components and Technology Conference (ECTC) in San Diego last month.<\/p>\n

\u201cWith need to put all of this in a framework,\u201d said Ravi Mahajan, an Intel<\/a> fellow. \u201cWith any new architecture, you need a way to bucket-ize it. And if the framework is defined well enough, you need to achieve consensus across the industry. So if you look at photonics, there\u2019s a fairly decent set of papers. But some of these use a silicon interposer, some use a bridge, and some are using organic interposers, which are catching up to the others. There are differences in the densities. We also see glass interposers coming into the market.\u201d<\/p>\n

\"\"<\/a>
\nFig. 2: Multiple options, with more on the way. (Swift, SLIM are trademarks of Amkor; FoCoS is trademarked by ASE; CoWoS and InFO are TSMC trademarks.) Source: IEEE\/Swaminathan<\/strong><\/p>\n

But all of this can at least be grouped together, which is what foundries and packaging houses are trying to do. In the past, much of this was developed ad hoc with little concern for nomenclature. This happened largely because advanced packaging was off to the sidelines of the main event, which was shrinking features at each new process node. But at 10\/7nm and beyond, the benefits of scaling are shrinking while costs are rising. Even with new transistor structures, the kind of gains that shrinking brought in the past are no longer possible.<\/p>\n

\u201cBefore 14nm, there was a 30% improvement in price\/performance at each node,\u201d said ES Jung, executive vice president and general manager of the foundry business in Samsung<\/a>\u2018s Device Solutions Division. \u201cFrom 14nm to 10nm, there is more than 20% improvement, and at less than 10nm there is more than 20%. At 3nm, there is about 20% improvement.\u201d<\/p>\n

There is no comparable measurement for advanced packaging, because many of the implementations are customized. But reports of 30% improvements in performance and power are not uncommon, which is why all of the high-speed networking and some of the new server chips utilize advanced packaging. Even Intel, which has been the gatekeeper of Moore\u2019s Law since it was first introduced, has begun offering advanced packaging options using its Embedded Multi-die Interconnect Bridge (EMIB) to shorten the distance between various components on a chip and to widen the signal channel, which both improves performance and requires less power to drive signals.<\/p>\n

This is becoming particularly important in applications where there is more data to contend with, such as AI<\/a> and machine learning<\/a>.<\/p>\n

\u201cWith AI, the key measurement is cost per function,\u201d said Subramanian Kengeri, vice president and general manager of the CMOS Platforms Business Unit at GlobalFoundries<\/a>. \u201cA lot of this is 2.5D and 3D, and heterogeneous integration is what everyone wants to see. The Holy Grail is to be able to get everything onto a monolithic SoC, but when you\u2019re adding MRAM, analog from older nodes, there is no single technology node that allows you to add all of the functionality. So you\u2019re going to be using multiple chips, and what you want to do is take the minimal number of chips and integrate them together with some packaging technology.\u201d<\/p>\n

Different approaches<\/strong>
\nThis is an architectural challenge, and different companies are using different architectures and components depending on what they are trying to achieve and the type of data they are working with. For example, Facebook is more concerned with image processing and recognition, while Google is more focused on search data. No two problems are the same, and that is reflected in the packages. Some are more focused on thermal dissipation, others on performance or power, or some combination of all of those.<\/p>\n

The result is that no two packages are exactly alike. The result is that no two packages are exactly alike. \u201cAdvanced packaging platforms enable solutions for diverse applications ranging from mobile to high performance computing,\u201d said Manish Ranjan, managing director of Lam Research<\/a>\u2018s Advanced Packaging Customer Operations. \u201cIDM, foundry and OSAT customers have developed various integration schemes for different end applications. Several technology platform solutions such as fan-out wafer level packaging, silicon interposer and TSVs will continue to co-exist for different end markets.\u201d<\/p>\n

TSMC<\/a> has skirted this issue somewhat by combining everything under the headings of InFO (Integrated Fan-Out) or CoWoS (Chip On Wafer On Substrate). Other foundries and OSATs<\/a> have begun offering their own branded terminology, as well. But figuring out how one differs from another isn\u2019t trivial, particularly for proprietary solutions.<\/p>\n

This is one of the reasons DARPA has been pushing chiplets, both for military and commercial applications. The idea that companies can build customized chips quickly is an interesting concept, but it will some time before there are enough options available to pick and choose from a variety of different IP vendors. Still, an increasing number of chipmakers are rallying beyind this option.<\/p>\n

\u201cOne of the advantages of chiplets is that you don\u2019t have to say what kind of package you\u2019re using,\u201d said Amin Shokrollahi, CEO of Kandou Bus, which develops chip-to-chip links and SerDes chiplets. \u201cPeople are talking about ways to implement them rather than how you actually put things together. The real key is that you have multiple dies connected together in some package. This gets around the taxonomy problem because you\u2019re looking at a higher level first. It\u2019s like trying to compare a convertible to an SUV. They\u2019re both still a car.\u201d<\/p>\n

Yaniv Kopelman, networking CTO and senior director at Marvell<\/a>, said he has been pushing this approach for the past couple of years. Marvell introduced its modular chip architecture, also known as MoChi, back in 2015. The idea was to select from a menu of options, then package it together using an interconnect fabric.<\/p>\n

\u201cFor the last two years, we have been trying to convince people this is the way to go,\u201d said Kopelman. \u201cThis has become one of the big topics recently because of the huge number of interfaces you need to support, particularly for applications like machine learning and AI. What\u2019s really critical is all of the OSATs already know how to do this, so there is no limit on the number or placement of dies. And it\u2019s cost-effective and open. It now uses a USR interface. A lot of the other solutions are semi-proprietary.\u201d<\/p>\n

Marvell more recently has been supporting the Cache Coherent Interconnect for Accelerators (CCIX) for connecting the various pieces together. \u201cThe key here is that this is known technology, not new proprietary interfaces,\u201d Kopelman said. \u201cProprietary interfaces cost more.\u201d<\/p>\n

They also add to the confusion about which path to choose going forward, from fan-out to 2.5D to system-in-package.<\/p>\n

\u201cHigh Density Fan Out Solutions are gaining traction for mobile and certain high performance computing segment,\u201d said Choon Lee, vice president of advanced packaging at Lam Research. \u201cManaging warpage and overall yield is critical to ramping next-generation fan out solutions in a cost-effective manner. It is expected that high-density fan out should also enable mixed die integration in a system-in-package<\/a> (SiP) format.\u201d<\/p>\n

\"\"<\/a>
\nFig. 3: CCIX architecture. Source: ccixconsortium.com<\/strong><\/p>\n

3D-ICs<\/strong>
\nWhile 3D-ICs have been on the drawing board for most of this decade, there has been little outward progress in this area. Initial designs were rejected because of thermal considerations. Logic on logic produces too much heat, so a processor sandwiched between other processors and memory would have to be powered down to the point where it would be less efficient than adding separate die into a different type of package.<\/p>\n

Memory on logic, however, has proven to be a workable scheme from a thermal standpoint, and chips are under development that leverage this model\u2014particularly with elements of programmability built in. That could include an embedded FPGA, multiple DSP elements, or some combination of both. The value proposition is that it prevents obsolescence for multiple chips in a package.<\/p>\n

There seems to be remarkably little confusion about 3D-ICs, in part because they\u2019re an all-in one solution. And while they can be constructed different ways, so far there is very little variation in the taxonomy.<\/p>\n

Nevertheless, 3D-ICs are a highly competitive battleground among a select group of processor vendors. While multiple companies are building them today, only the memory vendors are willing to talk about them.<\/p>\n

\"\"<\/a>
\nFig. 4: 3D-IC approach, with through-silicon vias. Source: Mentor, a Siemens Business<\/strong><\/p>\n

Conclusion<\/strong>
\nConcerns about naming conventions, and the confusion that spawned those concerns, are signs that the market is heating up in advanced packaging. When Apple introduced the iPhone 7, it was the first major company to embrace fan-out packaging. Since then, fan-outs and multiple versions of nearly everything else have gone mainstream.<\/p>\n

As with most new technologies and technology approaches, that initial explosion is followed by companies exploring every possible permutation to figure out what works best where and, ultimately for the best price. That almost certainly will lead to a winnowing-out phase, where the number of architectural choices is reduced and the number of companies vying for a piece of this market shrinks. But that still may be years away, and just how successful companies will be at defining the taxonomy in the short-term isn\u2019t entirely clear. What is clear is that advanced packaging is here to stay, no matter how it gets classified.<\/p>\n<\/div>\n

Source:\u00a0https:\/\/semiengineering.com<\/a><\/p>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n","protected":false},"excerpt":{"rendered":"

An interesting article from\u00a0 Ed Sterling at\u00a0semiengineering.com. Advanced packaging is exploding in all directions. There are more chipmakers utilizing different packaging options, more options for the packages themselves, and a confusing array of descriptions and names being used for all of these. Several years ago, there were basically two options on the table, 3D-ICs and […]<\/p>\n","protected":false},"author":1,"featured_media":2415,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"amp_status":"","_jetpack_memberships_contains_paid_content":false,"footnotes":"","jetpack_publicize_message":"Advanced Packaging Confusion #packaging #electronics #technology #material","jetpack_publicize_feature_enabled":true,"jetpack_social_post_already_shared":true,"jetpack_social_options":{"image_generator_settings":{"template":"highway","enabled":false}}},"categories":[242],"tags":[91,105,104,76],"jetpack_publicize_connections":[],"yoast_head":"\nAdvanced Packaging Confusion - AthisNews<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/athis-technologies.com\/news\/innovation\/manufacturing\/2018\/advanced-packaging-confusion\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Advanced Packaging Confusion - AthisNews\" \/>\n<meta property=\"og:description\" content=\"An interesting article from\u00a0 Ed Sterling at\u00a0semiengineering.com. Advanced packaging is exploding in all directions. There are more chipmakers utilizing different packaging options, more options for the packages themselves, and a confusing array of descriptions and names being used for all of these. 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