{"id":1578,"date":"2018-05-31T11:48:16","date_gmt":"2018-05-31T11:48:16","guid":{"rendered":"https:\/\/athis-consulting.com\/news\/?p=1578"},"modified":"2018-09-14T21:10:37","modified_gmt":"2018-09-14T21:10:37","slug":"perspective-new-process-technologies-required-for-future-devices-and-scaling","status":"publish","type":"post","link":"https:\/\/athis-technologies.com\/news\/innovation\/manufacturing\/2018\/perspective-new-process-technologies-required-for-future-devices-and-scaling\/","title":{"rendered":"Perspective: New process technologies required for future devices and scaling"},"content":{"rendered":"<p class=\"full-name\">Robert D. Clark and his coauthors worked in an deep study which is an invited perspective on the new process technologies that will need to be developed in order to enable future semiconductor device scaling. It&#8217;s in the most recent issue of APL Materials.<\/p>\n<div class=\"hlFld-Abstract abstract-full-page\">\n<div class=\"abstractSection abstractInFull\">\n<div class=\"NLM_paragraph\">This paper presents an overview and perspective on processing technologies required for continued scaling of leading edge and emerging semiconductor devices. They introduce the main drivers and trends affecting future semiconductor device scaling and provide examples of emerging devices and architectures that may be implemented within the next 10-20 yr. They summarize multiple active areas of research to explain how future thin film deposition, etch, and patterning technologies can enable 3D (vertical) power, performance, area, and cost scaling. Emerging and new process technologies will be required to enable improved contacts, scaled and future devices and interconnects, monolithic 3D integration, and new computing architectures. These process technologies are explained and discussed with a focus on opportunities for continued improvement and innovation.<\/div>\n<\/div>\n<\/div>\n<div class=\"hlFld-Fulltext\">\n<div id=\"s1\" class=\"NLM_sec NLM_sec_level_1\">\n<div class=\"sectionInfo\"><\/div>\n<\/div>\n<\/div>\n<p><img decoding=\"async\" src=\"https:\/\/aip.scitation.org\/na101\/home\/literatum\/publisher\/aip\/journals\/content\/apm\/2018\/apm.2018.6.issue-5\/1.5026805\/20180527\/images\/medium\/1.5026805.figures.online.f1.jpg\" alt=\"Figure\" \/><\/p>\n<div id=\"s1\" class=\"NLM_sec NLM_sec_level_1\">\n<div id=\"extrafiglink-f1\" class=\"figure figure-image-content\">\n<div id=\"f1\" class=\"holder\">\n<div class=\"caption\">\n<div class=\"NLM_paragraph\"><span class=\"captionLabel\">FIG. 1.<\/span>Illustration of the migration to 3D devices and 3D architectures taking place in the semiconductor industry. (note: IDM is an integrated device maker).<\/div>\n<div><\/div>\n<\/div>\n<div><img decoding=\"async\" src=\"https:\/\/aip.scitation.org\/na101\/home\/literatum\/publisher\/aip\/journals\/content\/apm\/2018\/apm.2018.6.issue-5\/1.5026805\/20180527\/images\/medium\/1.5026805.figures.online.f2.jpg\" alt=\"Figure\" \/><\/div>\n<div><span class=\"captionLabel\">FIG. 2.<\/span>Illustration of a self-aligned quadruple patterning (SAQP)\u00a0flow with unidirectional lines and multiple cut masks. Dense lines and space patterns are initially formed by SAQP, and then multiple cuts or trim masks with very fine isolated features are used to cut the lines into useful device features or wiring.\u00a0The EPE is a function of the critical dimension (CD) variation as well as the pattern overlay (OL) error for each mask.<\/div>\n<div><\/div>\n<\/div>\n<div><img decoding=\"async\" src=\"https:\/\/aip.scitation.org\/na101\/home\/literatum\/publisher\/aip\/journals\/content\/apm\/2018\/apm.2018.6.issue-5\/1.5026805\/20180527\/images\/medium\/1.5026805.figures.online.f3.jpg\" alt=\"Figure\" \/><\/div>\n<div><span class=\"captionLabel\">FIG. 3.<\/span>Cross-sectional schematic illustrating the multi-color approach to SAGC integration. GC and SD arrows indicate relative EPE tolerances for gate contact (GC) and source\/drain (SD) contact placement, respectively. The gate cap and SD cap are dielectric capping layers that can be etched away selectively,<span class=\"ref-lnk\"><a href=\"https:\/\/aip.scitation.org\/doi\/10.1063\/1.5026805#\" data-rid=\"c7\" data-reflink=\"_i18\"><sup>7<\/sup><\/a><i><\/i><\/span>\u00a0so if an SD contact lands partially on a gate cap, the gate cap will prevent a short. See also Fig.\u00a0<span id=\"ref-f4\" class=\"figure refFigure figuresContent\">4.<\/span><\/div>\n<\/div>\n<\/div>\n<p><a href=\"https:\/\/aip.scitation.org\/doi\/10.1063\/1.5026805\" target=\"_blank\" rel=\"noopener\">Full Article<\/a><\/p>\n<p>Source:\u00a0<a href=\"https:\/\/aip.scitation.org\" target=\"_blank\" rel=\"noopener\">https:\/\/aip.scitation.org<\/a><\/p>\n<p>Featured Image credit:\u00a0steve curd<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Robert D. Clark and his coauthors worked in an deep study which is an invited perspective on the new process technologies that will need to be developed in order to enable future semiconductor device scaling. It&#8217;s in the most recent issue of APL Materials. This paper presents an overview and perspective on processing technologies required [&hellip;]<\/p>\n","protected":false},"author":3,"featured_media":1767,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"amp_status":"","_jetpack_memberships_contains_paid_content":false,"footnotes":"","jetpack_publicize_message":"","jetpack_publicize_feature_enabled":true,"jetpack_social_post_already_shared":true,"jetpack_social_options":{"image_generator_settings":{"template":"highway","enabled":false}}},"categories":[242],"tags":[],"jetpack_publicize_connections":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v22.8 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Perspective: New process technologies required for future devices and scaling - AthisNews<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/athis-technologies.com\/news\/innovation\/manufacturing\/2018\/perspective-new-process-technologies-required-for-future-devices-and-scaling\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Perspective: New process technologies required for future devices and scaling - AthisNews\" \/>\n<meta property=\"og:description\" content=\"Robert D. Clark and his coauthors worked in an deep study which is an invited perspective on the new process technologies that will need to be developed in order to enable future semiconductor device scaling. It&#8217;s in the most recent issue of APL Materials. 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